An Effective on-Chip Network Topology for Network on Chip (Noc) Trade-Offs
نویسندگان
چکیده
منابع مشابه
Interconnect intellectual property for Network-on-Chip (NoC)
As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network...
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Deterministic and adaptive distributed routing algorithms have been advocated in all the current NoC architectural proposals. In this paper we make a case for the use of source routing for NoCs, especially for regular topologies like mesh. The advantages of source routing include in-order packet delivery; faster and simpler router design; and possibility of mixing non-minimal paths in a mainly ...
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Simulation techniques cannot provide a complete analysis of Network-on-chip (NoC) architectures due to their reactive and distributive nature and thus compromise on the accuracy of the analysis results. Formal methods can be used to overcome these limitations but, to the best of our knowledge, have been used for the functional verification of packet-switched NoCs only. We propose to extend the ...
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ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2016
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2016/v9i17/93120